1. Field of Invention
This invention relates to an integrated circuit (IC) process, and particularly to an overlay mark applied in a lithography-etching-lithography-etching (LELE)-type double patterning lithography (DPL) process, and a method for forming the overlay mark.
2. Description of Related Art
In order to check the alignment accuracy between patterns of a previous wafer layer and patterns of a current wafer layer that is more important as the linewidth gets smaller, an IC wafer is usually formed with many overlay marks thereon.
Meanwhile, as the linewidth gets smaller, various double patterning processes are utilized to form dense patterns with a pitch smaller than the lithographic resolution. For example, the current layer may be patterned through a process including a first lithography step, a first etching step, a second lithography step and a second etching step in sequence, namely a LELE-type DPL process.
In such a process, conventionally, linear patterns defined by the first lithography step and linear patterns defined by the second lithography step are formed in two separate overlay mark regions respectively with different parts of linear patterns of the previous layer. Therefore, a larger wafer area is required for forming overlay marks.
Moreover, because the overlay errors of the two lithography steps are measured with respect to different parts of linear patterns of the previous layer in different overlay marks, the accuracy of the overlay errors measurement is lower.